A multi-process device may be described as a processing device that supports the concurrent execution of multiple computing processes. One example of a multi-process device may have multiple semiconductor integrated circuit hardware processors, each hardware processor capable of executing one or more physically concurrent computing processes. Another example of a multi-process device may include only a single hardware processor, but the single hardware processor may support the concurrent execution of multiple software/firmware based computing processes, e.g., using time-sliced execution. Still other multi-process devices may use multiple hardware processors that support the execution of multiple physically concurrent computing processes as well as the time-sliced execution of multiple computing processes.
Multi-process devices may be included in virtually any processor-based digital electronic device. Such products may include, but are not limited to: computing devices, such as computer servers, desktop computers, laptop computers and hand-held computers; communication devices, such as cell phones, digital radios and digital communication switches; consumer entertainment products such as digital televisions, digital versatile disc (DVD) players, digital cameras and digital camcorders; and control systems, such as control systems used in automobiles, aircraft, HVAC environmental controls and security systems.
Each process executed by a multi-process device requires the use of electronic memory to store one or more executable instructions, control parameters, input data for processing, intermediate data values generated as a result of the process and/or final output generated as a result of the process. However, due to space constraints, and/or to reduce complexity and thereby increase reliability and manufacturing process yields, semiconductor integrated circuit hardware processors, one or more of which may be integrated within a multi-process device, typically include only a limited amount of memory storage. Typically, a multi-process device will include one or more memory controllers, e.g., one or more direct memory access (DMA) controllers, that allow the processes executed by the multi-process device to use physical memory, e.g., synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR-SDRAM), static random access memory (SRAM), etc., that is located on an separately manufactured semiconductor integrated circuit. In this manner, a multi-process device may be configured with access to sufficient memory to meet the processing requirements of the multiple concurrently executing computing processes the multi-process device will support.
Processes executed by a multi-process device may communicate with each other by passing information and data between the respective processes. Such interprocess communication allows complex tasks performed by the multi-process device to be divided into less complex subtasks that may be performed by separate processes executed by the multi-process device. In such a configuration, the respective processes executed by a multi-processor device may communicate with each other to share status and/or intermediate and/or final processed results, as needed, to support the coordinated execution of a larger task.
Current techniques used for passing information and data between processes in a multi-process device are inefficient. For example, to support interprocess communication, existing techniques require that data be copied from a memory area controlled by a first process, or source process, to a memory area controlled by a second process, or destination process.
Such an interprocess communication approach is inefficient for several reasons, including but not limited to the following. First, such an interprocess communication approach increases the memory storage and bandwidth requirements of the multi-process device by requiring that data passed in interprocess communications be stored more than once. Second, the process of copying interprocess communication data from a first location to a second location requires processing and/or bus clock cycles that could otherwise be used for other purposes. Increasing the memory size and bandwidth requirements of a multi-process device increases the space and power requirements of the multi-process device. Further, increasing the processing cycles for the multi-process device to perform a task requires that, for time critical processes, the clock-speed of the multi-process device must be increased, thereby increasing the complexity and/or the power requirements of the multi-process device.
Further, current interprocess communication techniques rely on the respective processes in a multi-process device to self-manage their respective shared memory usage and do not provide enforcement mechanisms that prevent one process from overwriting or freeing memory belonging to, and in use by, another process. As a result, if one or more processes within a multi-process device do not properly self-manage their respective memory usage, the entire multi-process device may become unstable. In addition, such problems are difficult to detect and isolate.